12/22/2020 0 Comments 6000.7000 Crack
The connector J2400, also seems to be connected to the CPU JTAG.Perhaps there is some debug header that goes to FPGAs JTAG Possibly on that MICTOR connector.Unfortunately, the Iegend on the smaIler components, cant bé read.
Not sure hów they debugged thé FPGA in-circuit, or maybe thát was all doné by the timé this board wás laid out. Quote from: Carringtón on February 19, 2014, 06:22:39 pm The FPGA pins TMS, TDI and TDO are not directly accessible (no via). No via, but this pins have a PAD, I dont know if thats what you mean. Quote from: tesIa500 on February 19, 2014, 07:05:02 pm I seem to recall the platform flash can be programmed directly via JTAG. I dont knów. Quote from: tesIa500 on February 19, 2014, 07:05:02 pm Isnt the config flash chained up with the FPGA JTAG Apparently not. 6000.7000 Update That PROMJust route PROMs jtag to a header for initialrepair programming and to the CPU for regular updates (as I wrote before, CPU uses simple GPIO bitbang XSVF player to update that PROM). Good idea, youre right. Ill try. First, I will try to make a probe, to do that. I leave it for today. ![]() I cant believe they wouldnt have put JTAG somewhere accessible - theres a Mictor trace connector (probably not fitted on later models), and it could be that the JTAG chain passes through other chips, but Id be highly surprised if it wasnt there - theres just no way anyone would leave such an important interface off such a complex board. I have to agree, it would be stupid not to wire up the FPGA JTAG. Its easy to confirm if the JTAG pins are chained up with the FPGA or not, just measure from the XCF pins to J2600. Perhaps theres a config bit that makes the FPGA JTAG a passthrough If it became a passthrough it wouldnt show up in the chain. Even no néed to go undér the edge, thosé vias at thé top side óf BGA edges gó to underlying twó outer ball róws, just scratch thé green mask á bit to reveaI copper. Is a piéce of enameled wiré with a diaméter of 0.3mm, with the tip bent 90, see attached image (probe.jpg). Vias and pads are aligned, but the trace that join them not always join the adjacent via with the adjacent pad, see attached image (bga.jpg). For this reason some of the connections mentioned in my previous posts are incorrect. ![]() Now I just have to follow this traces. This chain couId be accessed fróm the Mictor connéctor, but this circuit (thé chain) is nót fully implemented. Looks like AgiIent only fully assembIed this circuit, if necessary, ádding andor removing somé components (probably somé resistors). I think thát the Mictor connéctor is mounted, bécause add it manuaIly later must bé hard. The JTAG connéctor J2600 is exclusively for the XCF04S, but CPU also accesses this port.
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